When a peripheral unit provides data to be supplied to the central logic unit (CPU) or is ready to receive data, it notifies the CPU thereof via an interrupt request; i.e. the CPU is requested to halt its operative program and to activate the specific routines that supervise the dialogue with the peripheral unit.
It is desirable to promptly display all the interrupt requests without the need for an excessive amount of circuitry and software.
A sequential scanning of all the peripheral units (or, more precisely, of the interface circuits in the processor, each of which is bidirectionally associated with a peripheral unit) requires excessively long access time slots, even though it enables all the peripheral units to have, sooner or later, access to the CPU.
Wide spread use has been made of the so-called "daisy-chain" structure, wherein all the requests reach the CPU via a common line. Through a second common line, separate from the previous one the, CPU sends an enabling message which is transmitted over the interface circuits according to a prefixed priority code often determined by the physical position of the interface circuit in the frame (the unit adjacent the CPU is the first to receive the message enabling it to send its own identification code to the bus, and so on). Such a structure requires a very small number of wires but presents two serious drawbacks:
a low-priority peripheral unit is seldom served;
the absence or failure of a peripheral unit (or of the corresponding interface circuit) stops the handling of the interrupt relative to the peripheral units following the defective unit in the priority chain.